Tra cứu chân FPGA (ALINX AC7A035)
FPGA Pin Assignment Reference
CN1–CN4: tên tín hiệu, net bank, package pin (khi có XDC) và mô tả chức năng trên card HBQ.
CN1-CN4: signal name, bank net, package pin (when in XDC) and function on the HBQ card.
Thông số ModuleModule Specifications
XC7A35TArtix-7 / FGG484
4 x 80B2B connectors
-Dòng tín hiệuSignal rows
-Có package pinWith package pin
| Parameter | Value |
|---|---|
| FPGA Chip | Xilinx XC7A35T-2FGG484I (Artix-7 35K) |
| Logic Cells | 33,280 |
| DDR3 / Flash | 1GB DDR3 / 16MB QSPI |
| Clocks | 200 MHz system / 125 MHz GTP ref |
| B2B Interface | 4 x Panasonic AXK680337YG (80-pin) |
| IO | 146 x 3.3V + 15 x 1.5V + 4 GTP lanes |
| Power Input | 5V DC single supply via CN1 |
Sơ đồ ConnectorConnector Layout
Module kết nối base board qua 4 connector 80-chân (CN1–CN4). Package pin chỉ điền khi có trong XDC; các chân còn lại dùng net bank (Bxx_Lyy).
The module connects via four 80-pin connectors (CN1-CN4). Package pins are filled only when present in XDC; otherwise bank nets are shown.
| Connector | Banks | Main function |
|---|---|---|
| CN1 | B13, B34, B16 | Power, GPIO, XADC, CAN, Modbus, PCIe reset |
| CN2 | B13, B14, B16 | USB 3.0 32-bit data + control (FT601Q) |
| CN3 | B15, B16 | Motor, Encoder, DAC/ADC SPI, ISO IO, IMU, JTAG |
| CN4 | GTP, B16 | PCIe GTP lanes, FMC bus to STM32H7 |
Tra cứu chân nhanhMaster Pin Lookup
| CN Pin | Signal | FPGA Net | Package | Bank | Function |
|---|
CN1 - Power / GPIO / XADC / Fieldbus
| CN Pin | Signal | Net | Package | Bank | Function |
|---|
CN2 - USB 3.0 Data & Control
| CN Pin | Signal | Net | Package | Bank | Function |
|---|
CN3 - Motor / Encoder / Analog / ISO / JTAG
| CN Pin | Signal | Net | Package | Bank | Function |
|---|
CN4 - PCIe GTP & FMC Bus
| CN Pin | Signal | Net | Package | Bank | Function |
|---|
Cấu hình Bank I/OI/O Bank Configuration
| Bank | VCCO | IOSTANDARD | Description |
|---|---|---|---|
| B13/14/15/16 | 3.3V | LVCMOS33 | Main control / host IO |
| B34/35 | 1.5V / 3.3V | LVCMOS15 / var | XADC and special IO |
| GTP | 1.0V / 1.2V | DIFF_HSTL | PCIe high-speed lanes |
Lưu ý thiết kếDesign Notes
- CLOCK: Chân Y22 (USB_CLK) cần
CLOCK_DEDICATED_ROUTE FALSEtrong XDC. - CLOCK: Pin Y22 (USB_CLK) needs
CLOCK_DEDICATED_ROUTE FALSEin XDC. - POWER: VCCO banks 13-16 cố định 3.3V trên base board.
- POWER: VCCO for banks 13-16 is hardwired to 3.3V on the base board.
- PACKAGE: Chỉ các chân có trong XDC mới có package pin FGG484; các chân khác tra theo net bank.
- PACKAGE: Only XDC-constrained signals list FGG484 package pins; others use bank nets.
- XDC: fpga_alink_artix7_35K_pin_assignment.xdc